Apparatus for processing a signal to convert it from one form to another are well-known and are used for a variety of purposes. One type of apparatus is a strobed or sampling comparator circuit which has one operational mode for sampling an analog input signal and another operational mode for storing the sampled signal. The comparator circuit has an amplifying stage for amplifying the input signal and a storage stage for storing a sample of the amplified signal. An output stage of the comparator circuit then produces logic level signals in response to the stored signal.
One specific comparator circuit, implemented with MOS technology, is described in an article entitled A Highly Sensitive Strobed Comparator, by Akira Yukawa, IEEE Journal of Solid State Circuits, Vol. SC-16, No. 2, pp. 109-113, Apr., 1981. This comparator circuit has a first or input stage which is a differential amplifier for amplifying a differential voltage input signal, a second stage which is a strobed cross-coupled latch or flip-flop for storing and further amplifying the differential signal, and an intermediate stage which has depletion transistors for propagating the amplified signals from the differential amplifier to the latch and for limiting the current flow from the differential amplifier to the latch when the latter is strobed or enabled. The latch further amplifies the amplified signal received from the differential amplifier through the large gain of the latch applied in positive feedback. During the sampling mode, the latch is disabled or defeated, i.e., not strobed, and the differential input signal is continuously amplified by the amplifier, while in the storing mode the latch is enabled, i.e., strobed, to sample, store and further amplify the differential signal. An output stage of Yukawa then converts the stored signal to complementary logic levels.
One purpose of all such comparator circuits, including Yukawa, is to make an accurate comparison of small differential voltage input signals at high speed. Accuracy is achieved by employing the differential amplifier to amplify the small differential voltage input signal and employing the cross-coupled latch to amplify further this input signal through positive feedback. Such an accurate comparator circuit is said to be sensitive to the small differential voltages at its inputs.
In Yukawa, however, the speed of the MOS comparator circuit is constrained by the use of the intermediate stage of depletion transistors. As described in Yukawa, these depletion transistors are modeled as a resistive load for the latch which, together with the latch capacitance, provide an RC network that determines the speed of the signal processing or coupling between the differential amplifier and latch. The RC network provides signal delay which reduces the comparator circuit speed below optimum. This RC delay is in addition to signal delay caused by parasitic capacitances that electronic circuits inherently have.
Another type of strobed or sampling comparator circuit is disclosed in U.S. Pat. No. 3,843,934, by James N. Giles, issued Oct. 22, 1974 and assigned to the assignee of the present invention. This comparator circuit also includes a differential amplifier for amplifying a differential voltage input signal and a latch, having positive feedback, for further amplifying and storing the input signal. This comparator circuit is implemented in bipolar technology which is inherently faster than MOS technology and, therefore, does not have the same signal delay problems typically associated with MOS-type circuits.